As integrated circuits continue to evolve, lithography dimensions continue to decrease. Present day lithography is in the range of 0.1-0.2 micron. As a result, the semiconductor die continues to decrease in size. As a result of the decreased size of the semiconductor die, packaging issues are created that heretofore were non-existent. The decrease in semiconductor die size results in bond posts which are external to the die being removed farther and farther from the die in the semiconductor package, which encapsulates the die. As a result, the wires used to connect bond pads on the semiconductor die to bond posts in the package are becoming increasingly longer. Another issue is the high pin count resulting from increased integration afforded by the miniaturization. As a result of increased pin count, more pads per side of a package have to be included. The addition of pads to a side of an integrated circuit further increases the wire length because more bond posts have to be added farther from the side of the integrated circuit die.
Long wire length is problematic for several reasons. As first reason is the fact that long wire lengths result in many integrity problems such as shorting and wire sweep issues. Wire sweeping occurs when the encapsulant used to encapsulate the die is poured into a cavity and causes the wires to be swept in directions not anticipated. Additional issues with increased wire length include the degradation of electrical performance of the integrated circuit package.
As a result of these problems caused by increased wire length, package designers typically have a maximum wire length which cannot be exceeded in connection with implementing a package associated with the integrated circuit die.
Illustrated in FIG. 1 is a known integrated circuit package 10 having a die 12 with a plurality of bond pads, such as bond pads 13 and 14. Each bond pad has a bonding wire, such as bonding wire 16, connected to a respective bond post such as bond post 17. Bond post 17 is part of a conductive trace 18. As shown in FIG. 1, a respective bond pad is connected by a bonding wire to each bond post. From each bond post, a trace continues to the external periphery of the integrated circuit. It should be noted that integrated circuit package 10 has all of its bond posts orthogonal to a side of the integrated circuit die 12. As a result, all of the bonding wires, such as bonding wire 16, are connected substantially at a 90.degree. angle to the side of the integrated circuit die. Additionally, each of the bond posts are made larger than each conductive trace in order to allow more room for automatic wire bonding to the bond post. A disadvantage with the integrated circuit package 10 is that the orthogonal arrangement limits the amount of bonding wires which may be used on a side of an integrated circuit die. Note in particular that bond posts, such as bond post 17, are aligned or stacked essentially one along the other so that the number of bond posts per side of a die is limited by the width of the bond post and the required separation between each of the bond posts.
Illustrated in FIG. 2, is an integrated circuit package 20. Integrated circuit package 20 has a die 22 which has a plurality of bond pads, such as bond pads 24 and 25. From each bond pad is a bonding wire, such as bonding wire 26 or 28, connected to a respective bond post, such as bond post 27 or 29. Integrated circuit package 20 has the same disadvantage of using bond posts which are orthogonal to a side of die 22. As a result, a finite number of bond posts may be placed along the side of die 22 limited in number by the physical dimension of the side of die 22. The orthogonal staggered configuration is desirable only for low pin count packages. However, integrated circuit package 20 has the advantage over integrated circuit package 10 of having staggered bond posts. That is to say that not all of the bond posts are lined up along a same axis. As a result, an equal number of bond posts to the number of bond posts in integrated circuit package 10 may be placed in integrated circuit package 20 in a slightly smaller area. An example of an integrated circuit package such as integrated circuit package 20 is taught in U.S. Pat. No. 5,468,999, entitled "Liquid Encapsulated Ball Grid Array Semiconductor Device With Fine Pitch Wire Bonding," by Lin, et al., and assigned to the assignee hereof.
There remains a need for an integrated circuit package which has high pin count and small bond wire length for use with lithography dimensions which are approaching one-tenth of a micron. Existing packaging technologies continue to be limiting with respect to the advances made by integrated circuit integration. As integrated circuit dimensions have continued to decrease, the width required of a bond post in order to make a reliable bond has not decreased. As a result, existing packaging technologies have become inadequate for advanced semiconductor technologies.